1. Field of the Invention
The present invention relates to a class D amplifier that performs digital modulation and power amplification of an input PWM (Pulse Width Modulation) signal, and more particularly to a single-end-output class D amplifier that drives a load with one terminal grounded, as in the case of stereo headphones.
2. Description of the Related Art
Class D amplifiers are widely used as speaker drive amplifiers due to the fact that they feature extremely good power conversion efficiency, and thus a low level of heat discharge, compared with an analog linear amplifier such as a class A or B amplifier. A class D amplifier is implemented by performing switching operations by means of an amplification active element such as a transistor on an audio signal or suchlike input signal. A class D amplifier performs digital modulation of a PWM signal based on an input audio signal, performs power amplification of this PWM signal, and supplies the power amplified PWM signal to a speaker section.
A pulse modulation signal generation apparatus that prevents performance degradation due to harmonic distortion produced by PWM modulation in a fully digital amplifier is described in Patent Document 1 (Unexamined Japanese Patent Publication No. 2006-115028).
FIG. 1 is a drawing showing the configuration of a class D amplifier when driving stereo headphones.
In FIG. 1, class D amplifier 10 is configured by means of 8-fold oversampling circuits 11 and 12, ΔΣ modulation circuits 13 and 14, PWM circuits 15 and 16, level shifters (LS) 17, 18, and 23, D flip-flops 19 and 20, PWM output buffers 21 and 22, inductors 24 and 25, capacitors 26 through 29, 3-terminal connector 30, and stereo headphones 31. There are two of each configuration element in order to provide stereo output. To simplify the description, only one channel will be described. Operation is the same for both channels.
Input PCM data sampling frequency fs is increased 8-fold by 8-fold oversampling circuit 11.
ΔΣ modulation circuit 13 further increase the sampling frequency 2-fold, for a 16-fold increase in original sampling frequency fs. At the same time, requantization and noise shaping processing are performed.
PWM circuit 15 modulates M-ary output from ΔΣ modulation circuit 13 to a PWM wave. In this example, ΔΣ modulation circuit 13 is an M-ary output type, and requantizes to ±6—that is, 13—values. PWM circuit 15 generates a PWM wave such as shown in FIG. 2 according to this numeric value.
FIG. 2 is a drawing showing PWM circuit 15 output waveforms for ±6 values, and shows output steps that a PWM wave can take when the sampling rate is 16 fs.
Data of one sample is represented by 24 pulses of a clock signal. That is to say, the clock frequency is [384×fs].
As shown in FIG. 2, a PWM wave is at a high level for 24 clock pulses at ±6. At −6, the PWM wave is at a low level. At 0, the high-level period and low-level period are the same.
FIG. 3 shows signals at each of the above stages on the frequency axis.
FIG. 3 comprises drawings showing input PCM data, 8-fold oversampling, ΔΣ modulation circuit output, and a PWM wave on the frequency axis.
First, as shown in FIG. 3(a), modulation components up to [8×fs] above the first harmonic are eliminated by 8-fold oversampling of input PCM data.
Then, as shown in FIG. 3(b), ΔΣ modulation circuit 13 performs requantization and noise shaping processing by means of a [16×fs] sampling frequency. As a result, quantization noise is distributed with [8×fs] as a peak (see FIG. 3(c)).
PWM output buffer 21 is inserted in order to output a current capable of driving a load. PWM output buffer 21 output is at power supply voltage VDD at the high level and 0 V at the low level.
PWM output buffer 21 operates at power supply voltage VDD, unlike circuitry in the preceding stage. Therefore, PWM circuit 15 output is converted to a potential at which PWM output buffer 21 operates by means of level shifter 17. However, the waveform of a PWM wave may be disrupted by passage through level shifter 17. To prevent this, the PWM wave passes through D flip-flop 19. D flip-flop 19 operates at the same power supply voltage VDD as PWM output buffer 21, and therefore potential conversion is also performed for the clock in the same way as for the PWM wave by level shifter 23.
Inductor 24 and capacitor 26 form an LPF (Low Pass Filter).
FIG. 4 is a drawing showing a PWM waveform when ΔΣ modulation circuit 13 output is 0, and a waveform after passage through the LPF. As shown in FIG. 4, the high-level period and low-level period of a PWM wave are the same, and therefore the voltage after passage through the LPF is VDD/2.
Then stereo headphones 31 constituting the load are driven via capacitor 28 that cuts off direct current.
With typical stereo headphones, one side of the load is made common as ground. This enables the number of terminals of 3-terminal connector 30 to be kept to three.
However, a problem with a conventional class D amplifier of this kind is as follows.
One cause of degradation of class D amplifier performance is operating clock jitter.
FIG. 5 is a drawing explaining performance degradation of a class D amplifier due to operating clock jitter, showing a PWM waveform and voltage after passage through an LPF when ΔΣ modulation circuit 13 output is 0 in a case in which there is jitter in the operating clock. As shown in FIG. 5, when there is jitter in the operating clock, a perfect VDD/2 such as shown in FIG. 3 is not achieved, but instead noise is included.
To prevent this, a low-jitter clock source such as a crystal oscillation circuit is necessary.
However, a problem is that the crystal resonator of a crystal oscillation circuit is expensive in comparison with a part such as a resistor or capacitor.
Also, if there is a stable clock source of a different frequency, there is a method whereby a clock used by a class D amplifier is generated from that clock source using a PLL (Phase Locked Loop) circuit. However, since a low-jitter clock is necessary, as stated above, stringent performance requirements are imposed on the PLL circuit. This entails an increase in the operating power supply voltage of PLL circuit configuration elements such as a VCO (Voltage Controlled Oscillator) or charge pump.
Thus, with a class D amplifier that drives a load with one terminal grounded, such as stereo headphones, the use of an expensive part such as a crystal resonator has come to be a presupposition.